In integrated circuits (ICs), various devices such as logic devices and memory devices are configured to achieve the desired function. The memory devices and the logic devices surrounding the memory devices, for example, do not have substantially the same stack height across the same device. During fabrication of these devices, we have observed that the remaining gate electrode thickness which is suitable for forming, for example, the access gate or word line of the memory device is non-uniform across the edge and center regions of the memory array region. For example, we have found that a portion of the gate electrode layer at the edge of the memory array region is undesirably removed during a chemical mechanical polishing process (CMP) which is used to planarize the top surface of the gate electrode layer. The remaining gate electrode thickness at the edge of the memory array region is non-planar and includes a sloped profile relative to the remaining gate electrode thickness at the center region of the memory array region. The top surface of the remaining gate electrode layer at the edge of the memory array region, for example, is lower than that at the center region of the memory array region. This is undesirable as it may impact the yield.
From the foregoing discussion, it is desirable to have the remaining gate electrode thickness to be uniform across the different regions in an array region of the device.